Digital systems design using VHDL® / (Record no. 48361)

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008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 160825s2016 ohu 000 0 eng
010 ## - LIBRARY OF CONGRESS CONTROL NUMBER
LC control number 2016952395
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781305635142
040 ## - CATALOGING SOURCE
Original cataloging agency DLC
Language of cataloging eng
Description conventions rda
Transcribing agency DLC
041 ## - LANGUAGE CODE
Language code of text/sound track or separate title eng.
042 ## - AUTHENTICATION CODE
Authentication code pcc
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.392
100 1# - MAIN ENTRY--PERSONAL NAME
Preferred name for the person John, Lizy Kurian.
245 10 - TITLE STATEMENT
Title Digital systems design using VHDL® /
Statement of responsibility, etc Lizy Kurian John, Charles H. Roth, Jr.
250 ## - EDITION STATEMENT
Edition statement Third edition.
264 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc Boston, MA
Name of publisher, distributor, etc Cengage Learning,
Date of publication, distribution, etc [2018]
264 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Date of publication, distribution, etc c2018
300 ## - PHYSICAL DESCRIPTION
Extent xii, 628 pages :
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Dimensions 24 cm
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General note Charles H. Roth, Jr., University of Texas, Austin<br/>Charles Roth is Professor Emeritus in Electrical and Computer Engineering at the University of Texas at Austin, where he taught Digital Design for more than four decades. In addition to co-authoring DIGITAL SYSTEMS DESIGN USING VHDL, Dr. Roth has authored the successful FUNDAMENTALS OF LOGIC DESIGN and co-authored DIGITAL SYSTEMS DESIGN USING VERILOG.<br/>Lizy Kurian John, University of Texas, Austin<br/>Lizy John is the B. N. Gafford Professor in Electrical and Computer Engineering at the University of Texas at Austin. Dr. John has been teaching and conducting research in computer architecture and digital systems design for almost two decades. She has coauthored DIGITAL SYSTEMS DESIGN USING VHDL and DIGITAL SYSTEMS DESIGN USING VERILOG and has edited several successful books on computer performance evaluation and workload characterization. She is an IEEE Fellow.
505 ## - CONTENTS
Formatted contents note TABLE OF CONTENTS<br/>1. REVIEW OF LOGIC DESIGN FUNDAMENTALS.<br/>Combinational Logic. Boolean Algebra and Algebraic Simplification. Karnaugh Maps. Designing with NAND and NOR Gates. Hazards in Combinational Circuits. Flip-Flops and Latches. Mealy Sequential Circuit Design. Design of a Moore Sequential Circuit. Equivalent States and Reduction of State Tables. Sequential Circuit Timing / Tristate Logic and Busses.<br/>2. INTRODUCTION TO VHDL.<br/>Computer-Aided Design. Hardware Description Languages. VHDL Description of Combinational Circuits. VHDL Modules. Sequential Statements and VHDL Processes. Modeling Flip-Flops Using VHDL Processes. Processes Using Wait Statements. Two Types of VHDL Delays: Transport and Inertial Delays. Compilation, Simulation, and Synthesis of VHDL Code. VHDL Data Types and Operators. Simple Synthesis Examples. VHDL Models for Multiplexers. VHDL Libraries. Modeling Registers and Counters Using VHDL Processes. Behavioral and Structural VHDL. Variables, Signals, and Constants. Arrays. Loops in VHDL. Assert and Report Statements.<br/>3. INTRODUCTION TO PROGRAMMABLE LOGIC DEVICES.<br/>Brief Overview of Programmable Logic Devices. Simple Programmable Logic Devices (SPLDs). Complex Programmable Logic Devices (CPLDs). Field-Programmable Gate Arrays (FPGAs).<br/>4. DESIGN EXAMPLES.<br/>BCD to 7-Segment Display Decoder. A BCD Adder. 32-Bit Adders. Traffic Light Controller. State Graphs for Control Circuits. Scoreboard and Controller. Synchronization and Debouncing. A Shift-and-Add Multiplier. Array Multiplier. A Signed Integer/Fraction Multiplier. Keypad Scanner. Binary Dividers.<br/>5. SM CHARTS AND MICROPROGRAMMING.<br/>State Machine Charts. Derivation of SM Charts. Realization of SM Charts. Implementation of the Dice Game. Microprogramming. Linked State Machines.<br/>6. DESIGNING WITH FIELD PROGRAMMABLE GATE ARRAYS.<br/>Implementing Functions in FPGAs. Implementing Functions Using Shannon?s Decomposition. Carry Chains in FPGAs. Cascade Chains in FPGAs. Examples of Logic Blocks in Commercial FPGAs. Dedicated Memory in FPGAs. Dedicated Multipliers in FPGAs. Cost of Programmability. FPGAs and One-Hot State Assignment. FPGA Capacity: Maximum Gates Versus Usable Gates. Design Translation (Synthesis). Mapping, Placement, and Routing.<br/>7. FLOATING-POINT ARITHMETIC.<br/>Representation of Floating-Point Numbers. Floating-Point Multiplication. Floating-Point Addition. Other Floating-Point Operations.<br/>8. ADDITIONAL TOPICS IN VHDL.<br/>VHDL Functions. VHDL Procedures. Attributes. Creating Overloaded Operators. Multi-Valued Logic and Signal Resolution. The IEEE 9-Valued Logic System. SRAM Model Using IEEE 1164. Model for SRAM Read/Write System. Generics. Named Association. Generate Statements. Files and TEXTIO.<br/>9. DESIGN OF A RISC MICROPROCESSOR.<br/>The RISC Philosophy. The MIPS ISA. MIPS Instruction Encoding. Implementation of a MIPS Subset. VHDL Model.<br/>10. HARDWARE TESTING AND DESIGN FOR TESTABILITY.<br/>Testing Combinational Logic. Testing Sequential Logic. Scan Testing. Boundry Scan. Built-In Self-Test.<br/>11. ADDITIONAL DESIGN EXAMPLES.<br/>Design of a Wristwatch / Memory Timing Models. A Universal Asynchronous Receiver Transmitter (UART).<br/>Appendix A: VHDL Language Summary.<br/>Appendix B: IEEE Standard Libraries.<br/>Appendix C: TEXTIO Package.<br/>Appendix D: Projects.<br/>References.
520 ## - SUMMARY, ETC.
Summary, etc Written for an advanced-level course in digital systems design, Roth/John?s DIGITAL SYSTEMS DESIGN USING VHDL, 3E integrates the use of the industry-standard hardware description language VHDL into the digital design process. The book begins with a valuable review of basic logic design concepts before introducing the fundamentals of VHDL. The book concludes with detailed coverage of advanced VHDL topics.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Electronic digital computers
General subdivision Circuits
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element VHDL (Computer hardware description language)
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element System design
General subdivision Data processing.
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Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Permanent Location Current Location Shelving location Date acquired Source of acquisition Cost, normal purchase price Inventory number Full call number Barcode Date last seen Price effective from Item type
          COLLEGE LIBRARY COLLEGE LIBRARY SUBJECT REFERENCE 2017-09-04   7200.00 47926 621.392 R7422 2018 CITU-CL-47926 2020-05-23 2020-05-23 BOOK